In order to realize high integration of semiconductor integrated circuits, there has been used a method of layering a plurality of semiconductor integrated circuit chips (hereinafter “semiconductor chips”) to be a single package. An integrated circuit manufactured with use of such a method is called a three-dimensional integrated circuit. Patent Literatures 1 and 2 each disclose a three-dimensional integrated circuit design device that designs layout of each of a plurality of layered semiconductor chips constituting a semiconductor integrated circuit.
Layered first and second semiconductor chips constituting a three-dimensional integrated circuit are connected to each other through an electrode called a through-silicon via (TSV) penetrating the first semiconductor chip. Around the TSV, a placement prohibited region, which is a region where placement of a cell such as a transistor is prohibited, is placed. Also, a placement prohibition region is placed in a position of the second semiconductor chip corresponding to the position of the TSV of the first semiconductor chip. This is in order to prevent a stress, which occurs due to bonding of the first semiconductor chip and the second semiconductor chip, from exercising an influence on surrounding cells.